Recently, there has been a high level of activity using strained Si-based heterostructures to achieve high mobility structures for FET applications. Traditionally, the method to implement this has been to grow strained Si layers on a relaxed SiGe buffet. In this configuration, doping the SiGe layer leads to modulation doping of the tensile strained Si channel. Over the years, continual improvements in the buffer layers have led to an increase in the channel electron mobility to &gt;150,000 cm.sup.2 /Vs at 4.2.degree. K. However, there are several disadvantages to the growth of these thick buffer layers. First, as they are typically a micrometer to several micrometers thick, they are not easy to integrate with Si technology. Second, the defect density in these thick buffers is still high, about to 10.sup.4 to 10.sup.7 cm.sup.-2 which is too high for realistic VLSI consideration. Thirdly, the nature of the structure precludes selective growth of the SiGe so that circuits employing devices with strained Si, unstrained Si and SiGe material are difficult to integrate. This may be necessary since the strained Si channel is not usable as a high mobility hole channel and CMOS applications will not be optimized. Finally the high residual defect density may preclude obtaining the highest mobility possible. Besides the FET applications there is interest in relaxed buffer layers for other structures such as zone folding in monolayer type superlattices or resonant tunneling diodes.
In order to produce relaxed SiGe material on a Si substrate, conventional practice has been to grow a uniform, graded, or stepped, SiGe layer to beyond the metastable critical thickness (that is the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations, through the SiGe layer. Various buffer structures have been used to try to increase the length of the misfit dislocation sections in the structures and thereby reduce the threading dislocation density.